View MAX3815A_1237191.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. tmds digital video equalizer for hdmi/dvi cables MAX3815A general description the MAX3815A cable equalizer automatically provides compensation for dvi? and hdmi? v1.3 cables. it extends the usable cable distance up to 40 meters (1.65gbps) and 35 meters (2.25gbps). the MAX3815A is designed to equalize signals encoded in the transition- minimized differential signaling (tmds?) format. the MAX3815A features four cml-differential inputs and outputs (three data and one clock). it provides a loss-of- signal (los) output that indicates loss-of-clock signal. the outputs include a disable function. upon los, the chip is powered down. for direct chip-to-chip communi - cation, the output drivers can be switched to one-half the dvi output specification to conserve power and reduce emi. the output drive current can also be increased to allow the use of back termination resistors for improved signal integrity. equalization can be automatic or set to manual control for specific in-cable applications. the MAX3815A is available in a 7mm x 7mm, 48-pin tqfp-ep package and operates over a 0c to +70c temperature range. applications front-projector hdmi/dvi inputs high-definition televisions and displays hdmi/dvi-d cable-extender modules and active cable assemblies lcd computer monitors hdmi 1.3 deep color systems features s guaranteed performance to 2.25gbps (hdmi 1.3), improved jitter performance at low source amplitude, and enhanced output driver s extends 2.25gbps tmds interface length 0 to 35 meters over hdmi cable, 24 awg 0 to 22 meters over hdmi cable, 28 awg s extends 1.65gbps tmds interface length 0 to 40 meters over hdmi cable, 24 awg 0 to 28 meters over hdmi cable, 28 awg s compatible with hdtv resolutions 720p, 1080i, 1080p, and 1080p with 36-bit color s compatible with computer resolutions vga, svga, xga, sxga, uxga, and wuxga s fully automatic equalization, no system control required s 3.3v power supply s power dissipation of 0.6w (typ) s 7mm x 7mm, 48-pin tqfp lead-free package 19-4822; rev 0; 7/09 ordering information + denotes a lead(pb)-free/rohs compliant package. * ep = exposed pad. pin configuration appears at end of data sheet. typical operating circuits continued at end of data sheet. dvi is a trademark of digital display working group. hdmi is a trademark of hdmi licensing, llc. tmds is a registered trademark of silicon image inc. evaluation kit available video source up to 35m of hdmi or dvi cable st andard length dvi-d or hdmi cable hdmi or dvi extender box hdtv MAX3815A equalizer max3816a ddc extender part temp range pin-package MAX3815Accm+ 0 n c to +70 n c 48 tqfp-ep* typical operating circuits
tmds digital video equalizer for hdmi/dvi cables 2 ______________________________________________________________________________________ MAX3815A stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage range, v cc ................................ -0.5v to +4.0v voltage range at output cml pins ..................... -0.5v to +4.0v voltage range at input cml pins, res, vcc_t, and gnd_t ............................................ -0.5v to (v cc + 0.7v) voltage between input cml complementary pair ........... 3.3v voltage between output cml complementary pair ........ 1.4v continuous power dissipation (t a = +70c) 48-pin tqfp (derate 36.2mw/c above +70c) ........ 2896mw operating junction temperature range ......... -55c to +150c storage temperature range ............................ -55c to +150c die attach temperature .................................................. +400c absolute maximum ratings electrical characteristics (v cc = +3.0v to +3.5v, t a = 0c to +70c. typical values are at v cc = +3.3v, external terminations = 50 1%, MAX3815A in automatic equalization mode (eqcontrol = gnd), tmds rate = 250mbps to 2.25gbps, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units power-supply current i cc clock present (clklos = high) 210 270 ma clock and data absent (clklos = low) 12 supply-noise tolerance dc to 500khz 200 mv p-p equalizer performance residual output jitter (cables only) 0.25gbps to 1.65gbps (notes 1, 2, and 3) 1db skin-effect loss at 825mhz 0.05 ui 24db skin-effect loss at 825mhz 0.13 0.21 residual output jitter (cables only) 1.65gbps to 2.25gbps (notes 1, 2, and 3) 1db skin-effect loss at 825mhz 0.1 ui 24db skin-effect loss at 825mhz 0.14 0.28 cid tolerance 20 bits control and status clklos assert level differential peak-to-peak at eq input with max 225mhz clock (see the typical operating characteristics for more information) 50 mv p-p cml inputs (cable side) differential input-voltage swing v id at cable input 800 1000 1200 mv p-p common-mode input voltage v cm v cc - 0.4 v cc + 0.1 v input resistance r in single-ended 45 50 55 w cml outputs (asic side) differential output-voltage swing v od 50 w load, each side to v cc outlevel = high 800 1000 1200 mv p-p outlevel = low 500 with back termination as shown in figure 4, outlevel = open 910 output-voltage high single-ended, outlevel = high v cc mv output-voltage low single-ended, outlevel = high v cc - 600 v cc - 400 mv output voltage during clock absence (clklos = low) single-ended v cc - 10 v cc + 10 mv
tmds digital video equalizer for hdmi/dvi cables _______________________________________________________________________________________ 3 MAX3815A electrical characteristics (v cc = +3.5v to +3.5v, t a = 0c to +70c. typical values are at v cc = +3.3v, external terminations = 50 1%, MAX3815A in automatic equalization mode (eqcontrol = gnd), tmds rate = 250mbps to 2.25gbps, t a = +25c, unless otherwise noted.) note 1: ac specifications are guaranteed by design and characterization. note 2: cable input swing is 800mv to 1200mv differential peak-to-peak. residual output jitter is defined as peak-to-peak jitter, both deterministic plus random, as measured using an oscilloscope histogram with 5000 hits. source jitter subtracted. note 3: test pattern is a 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros. typical operating characteristics (typical values are at v cc = +3.3v, t a = +25c, data pattern = 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1v p-p differential, unless otherwise noted.) supply current vs. ambient temperature MAX3815A toc02 ambient temperature (c) supply current (ma) 60 50 30 40 20 10 160 170 180 190 200 210 220 230 240 250 150 0 70 outlevel = open, eqcontrol = v cc , clock signal active tmds source dc-coupled to MAX3815A input (nominal amplitude) tmds source ac-coupled to MAX3815A input return loss vs. frequency MAX3815A toc02 frequency (mhz) gain (db) 2500 2000 500 1000 1500 -35 -30 -25 -20 -15 -10 -5 0 -40 0 3000 parameter symbol conditions min typ max units common-mode output voltage 50 w load, each side to v cc , outlevel = high v cc - 0.25 v rise/fall time (note 1) 20% to 80% 80 160 ps lvttl control and status interface lvttl input high voltage v ih 2.0 v lvttl input low voltage v il 0.8 v lvttl input high current v ih(min) < v in < v cc 50 a lvttl input low current gnd < v in < v il(max) -100 a open-collector output high voltage r load 10k w to v cc 2.4 v open-collector output low voltage r load 2k w to v cc 0.4 v open-collector output sink current 5 ma outlevel input open-state current tolerance 5 a
tmds digital video equalizer for hdmi/dvi cables 4 ______________________________________________________________________________________ MAX3815A equalizer input after 100ft of 26 awg cable (top) equalizer output (bottom) MAX3815A toc03 5ns/div 20mv/div data rate = 2.25gbps 30db cable skin-effect loss at 1.11ghz 500mv/div equalizer input eye after 100ft of 26 awg cable (top) equalizer output (bottom) MAX3815A toc04 100ps/div 350mv/div data rate = 2.25gbps 30db cable skin-effect loss at 1.11ghz equalizer input eye after 150ft of 26 awg cable (top) equalizer output (bottom) MAX3815A toc05 300ps/div 350mv/div data rate = 742.5mbps 24db cable skin-effect loss at 370mhz total jitter vs. data rate (50m hdmi cable) MAX3815A toc06 data rate (mbps) total jitter (ps p-p ) 1750 1250 750 20 40 60 80 100 120 140 160 180 200 0 total jitter (ui p-p ) 0.1 0.2 0.3 0.4 0.5 0 250 2250 dvigear shr? hdmi cable (22 awg) peak-to-peak jitter in picoseconds peak-to-peak jitter in unit intervals total jitter vs. power-supply noise frequency (data rate = 2.25gbps) MAX3815A toc07 frequency (khz) total jitter (ps p-p ) 1000 100 10 110 120 130 140 150 160 170 180 100 1 10,000 noise amplitude: 200mv p-p data through 50m dvigear shr hdmi cable, 22 awg typical operating characteristics (continued) (typical values are at v cc 33v, t a 25c, data pattern 2 7 - 1 prbs 20 ones 2 7 - 1 prbs (inverted) 20 zeros, equalizer in automatic mode, cable launch amplitude 1v p-p differential, unless otherise noted) shr is a trademark of dvigear, inc
tmds digital video equalizer for hdmi/dvi cables _______________________________________________________________________________________ 5 MAX3815A typical operating characteristics (continued) (typical values are at v cc = +3.3v, t a = +25c, data pattern = 2 7 - 1 prbs + 20 ones + 2 7 - 1 prbs (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1v p-p differential, unless otherwise noted.) total jitter vs. cable length (carlisle interconnect technologies twin-ax 28 awg) MAX3815A toc08 cable length (m) deterministic jitter (ui p-p ) 30 20 10 0.1 0.2 0.3 0.4 0.5 0.6 0 0 40 2.25gbps no eq with MAX3815A eq 1.485mbps 742.5mbps total jitter vs. signal amplitude input to cable (data rate 2.25gbps) MAX3815A toc09 differential amplitude (v p-p ) total jitter (ps p-p ) 1.4 1.2 0.6 0.8 1.0 60 70 80 90 100 110 120 130 50 0.4 1.6 50m of dvigear shr hdmi cable with 35db loss at 1.11ghz eqcontrol voltage (relative to v cc ) vs. cable length (manual eq control) cable length (m) eqcontrol voltage (v) 20 10 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -0.8 0 30 cable is carlisle interconnect technologies twin-ax 28 awg with approximately 1.35db of loss per meter at 1.11ghz MAX3815A toc10 residual jitter (ps p-p ) 0 20 40 60 80 100 120 140 160 180 200 eqcontrol voltage residual jitter at 2.25gbps loss-of-clock assert threshold vs. cable length MAX3815A toc11 cable length (m) differential clock amplitude (mv p-p ) 30 24 18 12 6 50 100 150 200 250 300 350 0 0 36 clock amplitude is at input of cable cable is carlisle interconnect technologies twin-ax, 28 awg 225mhz clock frequency 25mhz clock frequency equalizer output eye after 50m of 22 awg hdmi cable (data rate = 2.25gbps) MAX3815A toc12 100ps/div 200mv/div dvigear shr hdmi cable
tmds digital video equalizer for hdmi/dvi cables 6 ______________________________________________________________________________________ MAX3815A pin description pin name function 1, 4, 5, 8, 9, 12, 13, 16, 38 v cc supply voltage. all pins must be connected to v cc . 2 rx0_in- negative data input, cml 3 rx0_in+ positive data input, cml 6 rx1_in- negative data input, cml 7 rx1_in+ positive data input, cml 10 rx2_in- negative data input, cml 11 rx2_in+ positive data input, cml 14 rxc_in+ positive clock input, cml 15 rxc_in- negative clock input, cml 17 eqcontrol equalizer control. this pin allows the user to control the equalization level of the MAX3815A. connect the pin to gnd for automatic operation. set the voltage to v cc /2 for minimum equalization, or set the voltage between v cc - 1v to v cc for manual equalization. see the applications information section for more information. 18 clklos loss-of-clock signal output, lvttl open collector. this pin asserts low upon loss of the input tmds clock from the cable. connect pin to v cc through a 4.7k resistor. 19 n.c. not connected. this pin is not internally connected. 20, 23, 24, 25, 28, 29, 32, 33, 36, 37 gnd ground 21 rxc_out- negative clock output, cml 22 rxc_out+ positive clock output, cml 26 rx2_out+ positive data output, cml 27 rx2_out- negative data output, cml 30 rx1_out+ positive data output, cml 31 rx1_out- negative data output, cml 34 rx0_out+ positive data output, cml 35 rx0_out- negative data output, cml 39 outlevel output-level control input ? high: standard swing (1000mv p-p ) differential ? open: standard swing (900mv p-p differential) with external 267 back termination resistor (see figure 4) ? low: one-half standard swing (500mv p-p differential) 40 outon output-enable control input, lvttl. this input enables the cml outputs when forced low and sets a differential logic zero when forced high. 41, 43, 44 vcc_t reserved. must be connected to v cc for normal operation. 42 gnd_t reserved. must be connected to gnd for normal operation. 45C48 res reserved. must be left open for normal operation. ep exposed pad. the exposed pad must be soldered to the circuit-board ground for proper thermal and electrical operation.
tmds digital video equalizer for hdmi/dvi cables _______________________________________________________________________________________ 7 MAX3815A detailed description the MAX3815A tmds equalizer accepts differential cml input data at rates of 250mbps up to 2.25gbps (individual channel data rate). it automatically adjusts to skin-effect losses in copper cable. it consists of four cml input buffers, a loss-of-clock signal detector, three independent adaptive equalizers, four limiting amplifiers, and four output buffers (figure 1). cml input buffers and output drivers the input buffers and the output drivers are implemented using current-mode logic (cml) (see figures 4 and 5). the output drivers are open-collector and can be turned off with the outon pin. the outlevel pin sets the output drive current to one of three levels; see the applications information and pin description sections for more infor - mation. for details on interfacing with cml, refer to application note 291: hfan-01.0: introduction to lvds, pecl, and cml . loss-of-clock signal detector the loss-of-clock signal detector indicates a loss-of- clock signal at the clklos pin. this is an open-collector output that must be connected to v cc through a 4.7k external pullup. this resistor is required whether or not the los output is used. adaptive equalizer the three data channels each contain an independent adaptive equalizer. each channel analyzes the incom - ing signal and determines the amount of equalization to apply. limiting amplifier the limiting amplifier amplifies the signal from the adap - tive equalizer and truncates the top and bottom of the waveform to provide a clean high- and low-level signal to the output drivers. figure 1. functional diagram input buffer driver adaptive eq limiting amplifier terminated 3.3v cml input buffer driver adaptive eq limiting amplifier terminated 3.3v cml input buffer driver adaptive eq limiting amplifier terminated 3.3v cml input buffer driver limiting amplifier terminated 3.3v cml rxc_out+/- outlevel rx2_out+/- rx1_out+/- rx0_out+/- rx0_in+/- rx1_in+/- rx2_in+/- rxc_in+/- clklos eqcontrol outon clock los detector MAX3815A
tmds digital video equalizer for hdmi/dvi cables 8 ______________________________________________________________________________________ MAX3815A applications information typical shielded twisted pair (stp), unshielded twisted pair (utp), and twin-ax cables exhibit skin-effect losses, which attenuate the high-frequency spectrum of a tmds signal, eventually causing data errors or even closing the signal eye altogether given a long enough cable. the MAX3815A recovers the data and opens the signal eye through compensating equalization. the basic tmds interface is composed of four differential serial links: three links carry serial data up to 2.25gbps each, and the fourth is a one-tenth-rate (0.1x) clock that operates up to 225mhz. tmds, as with analog nvga links, must handle a variety of resolutions and screen update rates. the actual range of digital serial rates is roughly 250mbps to 2.25gbps. for applications requir - ing ultra-high resolutions (e.g., qxga), a dual-link dvi interface is used and is composed of six data links plus the clock, requiring two MAX3815A ics with the clock going to both ics. see figure 2. the MAX3815A can be used to extend any tmds inter - face as used under the following trademarked names: dvi (digital visual interface), dfp? (digital flat-panel), panellink, adc? (apple display connector), and hdmi (high-definition multimedia interface). loss-of-clock signal ( clklos ) output a loss-of-clock signal is indicated by the clklos out - put. a low level on clklos indicates that the signal power on the rxc_in pins has dropped below a thresh - old. when there is sufficient input voltage to the channel (typically greater than 100mv p-p differential), clklos is high. the clklos output is suitable for indicating prob - lems with the transmission link caused by, for example, a broken cable, a defective driver, or a lost connection to the equalizer. note that the loss-of-clock circuitry is sensitive to a dc or ac voltage between the rxc_in pins. a dc or ac voltage greater than q 30mv (typical) is sensed as an active clock signal. figure 2. connection scheme for MAX3815A in dual link application dfp is a trademark of video electronics standards association (vesa). adc is a trademark of apple computer, inc. figure 4. back termination circuit figure 3. simplified clklos output circuit schematic d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 clk clk MAX3815A MAX3815A MAX3815A rx_out - 267 50 +3.3v 50 rx_out+ 12.5ma hdm/dvi receiver v cc v cc clklos to chip power- control circuitry 4.7k MAX3815A
tmds digital video equalizer for hdmi/dvi cables _______________________________________________________________________________________ 9 MAX3815A the loss-of-clock circuitry powers down the part when - ever there is an absence of a clock signal. this mutes the output and reduces power consumption to 83mw whenever the input signal is removed. during power- down, the MAX3815As tmds output pins go to a high- impedance state. the clklos is an open-collector output that requires a resistive pullup to v cc for operation. the pullup resistor range is 1k to 10k (see figure 3). output level control (outlevel) input the outlevel pin is a three-state input that allows the user to select between three output settings. forcing this pin high results in the standard output signal level with no back terminations; leaving the pin open results in a standard output swing with 267 differential back termi - nation resistors. forcing this pin low results in one-half standard output signal level. using back termination using back termination resistance improves signal integ - rity through absorption of reflections. it also shifts the sin - gle-ended output voltage high (v h ) and low (v l ). table 1 shows the output voltages when using the MAX3815A in each of its three output configurations. equalizer control (eqcontrol) input the eqcontrol pin allows the user to control the equalization in one of two ways: forcing the pin to ground sets the equalizer in automatic equalization mode, and forcing a voltage between v cc - 1v to v cc allows manual control of the equalization level. set to v cc for maximum boost (long cable). set to v cc - 1v for mini - mum boost (short cable). interface models figure 5. simplified input circuit schematic figure 6. simplified output circuit schematic table 1. output settings and swings v cc rx_in+/- 50 MAX3815A MAX3815A rx_ou t- pwrdwn 0 1 rx_out+ 10ma outlevel = high 12.5ma outlevel = open 5ma outlevel = low transient supressor clamp outlevel back termination differential swing (mv p-p ) single-ended high (v h ) single-ended low (v l ) high open 1000 v cc v cc - 500mv open 267 i 910 v cc - 85mv v cc - 540mv low open 500 v cc v cc - 250mv
tmds digital video equalizer for hdmi/dvi cables 10 _____________________________________________________________________________________ MAX3815A output on ( outon ) input the outon pin is an lvttl input. force the pin low to enable the outputs. force the pin high to set a differen - tial zero on the outputs, irrespective of the signal at the inputs. cable selection tmds performance is heavily dependent on cable quality. deterministic jitter (dj) can be caused by differential-to- common-mode conversion (or vice versa) within a twisted pair (stp or utp), usually a result of cable twist or dielectric imbalance. refer to application note 3353: hfan-04.5.4: jitter happens when a twisted pair is unbalanced and application note 4218: unbalanced twisted pairs can give you the jitters! for more information. layout considerations the data and clock inputs are the most critical paths for the MAX3815A and great care should be taken to mini - mize discontinuities on these transmission lines between the connector and the ic. here are some suggestions for maximizing the performance of the MAX3815A: ? the data and clock inputs should be wired directly between the cable connector and ic without stubs. ? place supply filter capacitors close to the MAX3815A inputs to provide a low inductance path for supply return currents. ? input and output data channel designations are only a guide. polarity assignments can be swapped and channel paths can be interchanged. ? an uninterrupted ground plane should be positioned beneath the high-speed i/os. ? ground-path vias should be placed close to the input/ output connectors to allow a low inductance return current path. ? maintain 100 differential transmission line impedance into and out of the MAX3815A. ? use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize emi and crosstalk. refer to application note 3854: max3815: interfacing to the max3815 dvi/hdmi cable equalizer and the ev kit data sheet, MAX3815Aevkit-hdmi. exposed-pad package the exposed pad on the 48-pin tqfp-ep provides a very low thermal resistance path for heat removal from the ic. the pad is also electrical ground on the MAX3815A and must be soldered to the circuit board ground for proper thermal and electrical performance. refer to maxim application note 862: hfan-08.1: thermal considerations of qfn and other exposed-paddle packages for additional information. chip information process: sige bipolar package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . figure 7. cable reach typical MAX3815A cable reach (data rate = 2.25gbps) wire gauge (awg) cable length (m) 24 26 10 20 30 40 50 60 0 28 22 typical limit of cable with eq at 2.25gbps typical limit of cable without eq at 2.25gbps package type package code document no. 48 tqfp-ep c48e+8 21-0065
tmds digital video equalizer for hdmi/dvi cables maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 11 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX3815A pin configuration rgb/hv adc/sync tmds deserializer select image scaler and processor panel interface timing and drivers lcd, dlp, or lcos vga input dvi-d input dvi-d cable up to 35m or 120ft (24 awg stp) laptop video projector equalizer MAX3815A 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 v cc rx0_in- rx0_in+ v cc v cc rx1_in- rx1_in+ v cc v cc rx2_in- rx2_in+ v cc res res res res vcc_t vcc_t gnd_t vcc_t outlevel v cc gnd gnd rx0_out- rx0_out+ gnd gnd rx1_out- rx1_out+ gnd gnd rx2_out- rx2_out+ gnd v cc rxc_in+ rxc_in- v cc eqcontrol gnd rxc_out- rxc_out+ gnd gnd clklos n.c. outon top view *ep *exposed pad. tqfp + MAX3815A typical operating circuits (continued)

▲Up To Search▲

Price & Availability of MAX3815A

	To Download MAX3815A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .